View MP7529A_165561.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MP7529A
15 V CMOS Dual Buffered Multiplying 8-Bit Digital-to-Analog Converter
FEATURES
* * * * * * * * * * Very Low Total Harmonic Distortion Lower Glitch Energy Four Quadrant Multiplication On-Chip Latches for Both DACs +10.8 V to +15.75 V Operation Low Power Consumption TTL/5V CMOS Compatible Latch-Up Free Second Source to AD7628 5 V Operation: MP7529B
BENEFITS
* Quiet Operation in Audio Applications * Easy Interface to Microprocessors
GENERAL DESCRIPTION
The MP7529A is a dual 8-bit Digital-to-Analog Converter featuring excellent DAC-to-DAC matching, tracking and specifically optimized for applications requiring low total harmonic distortion. The MP7529A is manufactured using advanced thin film resistors on a double metal CMOS process. The MP7529A incorporates a unique decoding technique yielding lower glitch energy, higher speed and excellent accuracy over temperature and time.
Data is transferred to either of the two D/A Converter latches via a common 8-bit TTL/5 V CMOS compatible input port. The control input DAC A/DAC B determines which DAC is to be loaded. The device is specified for operation from +10.8 V to +15.75 V power supply, and is TTL-compatible over this range. Power dissipation is only 20 mW. Both DACs offer excellent four quadrant multiplication characteristics, and include separate reference inputs and feedback resistors. An improved latch-up resistant design eliminates the need for external protective Schottky diodes in most applications.
www..com
SIMPLIFIED BLOCK AND TIMING DIAGRAM
VDD VREFA DB7-DB0 DAC A/DAC B CS WR RFBB D Q LATCH B E DAC B IOUTB AGND OUT
RFBA DB7-DB0 DAC A/DAC B D Q LATCH A E DAC A IOUTA
CS WR
DGND
VREFB
Rev. 2.00 1
MP7529A
ORDERING INFORMATION
Package Type
Plastic Dip Plastic Dip SOIC SOIC PLCC PLCC
Temperature Range
-40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C
Part No.
MP7529AJN MP7529AKN MP7529AJS MP7529AKS MP7529AJP MP7529AKP
INL (LSB)
+1 +1/2 +1 +1/2 +1 +1/2
DNL (LSB)
+1 +1 +1 +1 +1 +1
Gain Error (LSB)
+5 +3 +5 +3 +5 +3
PIN CONFIGURATIONS
See Packaging Section for Package Dimensions
IOUTB IOUTA AGND RFBA RFBB
3 2 1 20 19
AGND IOUTA RFBA VREFA DGND DAC A/DAC B (MSB) DB7 DB6 DB5 DB4
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
IOUTB RFBB VREFB VDD WR CS DB0 (LSB) DB1 DB2 DB3
1 2 3 4 5 6 7 8 9 10
20 19 18
VREFA DGND DAC A/DAC B (MSB) DB7 DB6
4 5 6 7 8
18 17 16 15 14
VREFB VDD WR CS DB0 (LSB)
See Pin Out at Left
17 16 15 14 13 12 11
9
10
11
12
13
DB5 DB3 DB1 DB4 DB2
20 Pin PDIP (0.300") N20
20 Pin SOIC (Jedec, 0.300") S20
20 Pin PLCC P20
www..com
PIN OUT DEFINITIONS
PIN NO. 1 2 3 4 5 6 7 8 9 10 NAME AGND IOUTA RFBA VREFA DGND DAC A/ DAC B DB7 DB6 DB5 DB4 DESCRIPTION Analog Ground Current Output of DAC A Internal Feedback Resistor of DAC A Reference Input Voltage of DAC A Digital Ground DAC selection control Data Input Input Bit 7 (MSB) Data Input Bit 6 Data Input Bit 5 Data Input Bit 4 PIN NO. 11 12 13 14 15 16 17 18 19 20 NAME DB3 DB2 DB1 DB0 CS WR VDD VREFB RFBB IOUTB DESCRIPTION Data Input Bit 3 Data Input Bit 2 Data Input Bit 1 Data Input Bit 0 (LSB) Chip Select (Active Low) Write Enable (Active Low) Power Supply Reference Input Voltage of DAC B Internal Feedback Resistor of DAC B Current Output of DAC B
Rev. 2.00 2
MP7529A
ELECTRICAL CHARACTERISTICS
(VDD = +10.8 V to +15.75, VREF = +10 V unless otherwise noted)
Parameter STATIC PERFORMANCE1 Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) J K Differential Non-Linearity J K Gain Error J K Gain Temperature Coefficient2 Power Supply Rejection Ratio Output Leakage Current DYNAMIC PERFORMANCE2 THD Q FT FTA FTB CCI CCIBA CCIAB Egl tS tPD -95 30 -70 -70 -77 -77 10 200 100 -65 -65 dB nVs dB dB dB dB dB dB nVs ns ns VIN = 6VRMS @ 1 kHz N INL +1 +1/2 DNL +1 +1 GE +4 +2 TCGE PSRR ILKG +15 +100 +50 +5 +3 +35 +200 +200 ppm/C ppm/% nA Gain/Temperature |Gain/VDD|, VDD = + 5% VDD = 10.8 V, +5%, & 15.75 V +5% +1 +1 LSB +1 +1/2 LSB All grades monotonic over full temperature range. Using Internal RFB 8 8 Bits LSB End Point Linearity Spec. Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments
Harmonic Distortion Digital Crosstalk AC Feedthrough VREFA to IOUTA VREFB to IOUTB Channel-to-Channel Isolation VREFA to IOUTB VREFB to IOUTA Glitch Energy Current Settling Time www..com Propagation Delay
250 150
All zeros to all ones Input Change To 1/2 LSB,RL=100, CEXT=13pF From 50% of digital input to 90% of final analog output current RL=100, CEXT=13pF
REFERENCE INPUT1 Input Resistance Input Resistance Matching DIGITAL INPUTS3 Logical "1" Voltage Logical "0" Voltage Input Leakage Current Input Capacitance2 Data Control VIH VIL ILKG CIN CIN 3.0 2.4 0.8 +1 10 15 3.0 0.8 +10 10 15 V V A pF pF RIN 8 15 +1 8 15 +1 k %
Rev. 2.00 3
MP7529A
ELECTRICAL CHARACTERISTICS (CONT'D)
Parameter ANALOG OUTPUTS2 Output Capacitance COUTA/B COUTA/B POWER SUPPLY1 Supply Current TIMING SPECIFICATIONS4 Chip Select to Write Set-Up Time Chip Select to Write Hold Time DAC Select to Write Set-Up Time DAC Select to Write Hold Time Data Valid to Write Set-Up Time Data Valid to Write Hold Time Write Pulse Width5 NOTES:
1 2 3 4 5
Symbol
Min
25C Typ
Max
Tmin to Tmax Min Max
Units
Test Conditions/Comments
120 50
120 50
pF pF
DAC inputs all 1's DAC inputs all 0's
IDD
1 2
1 2
mA mA
All digital inputs = 0 V, or all = 5 V All digital inputs = VIL, or all = VIH
tCS tCH tAS tAH tDS tDH tWR
60 15 60 15 60 0 60
80 20 80 20 80 0 80
ns ns ns ns ns ns ns
Full Scale Range (FSR) is 10V for unipolar mode. Guaranteed but not production tested. Digital input levels should not go below ground or exceed the positive supply voltage, otherwise damage may occur. See timing diagram Figure 1. tWR = 40ns minimum if tDH > 15ns (@T = 25C). Specifications are subject to change without notice
www..comMAXIMUM ABSOLUTE
RATINGS (TA = +25C unless otherwise noted)1, 2, 3
VRFBA, VRFBB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V Storage Temperature . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 seconds) . . . . . . +300C Package Power Dissipation Rating to 75C PDIP, SOIC, PLCC . . . . . . . . . . . . . . . . . . . . . . . . 900mW Derates above 75C . . . . . . . . . . . . . . . . . . . . . 12mW/C
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . GND -0.5 to +17 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V (Functionality Guaranteed +0.5 V) Digital Input Voltage to GND . . . . . . . . GND -0.5 V to +7 V IOUTA, IOUTB to GND . . . . . . . . . . . . . . . GND -0.5 V to +7 V VREFA, VREFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V
NOTES: 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100s. 3 GND refers to AGND and DGND.
Rev. 2.00 4
MP7529A
DIGITAL INTERFACE
The digital inputs are designed to be both TTL and 5 V CMOS compatible. All logic inputs are static protected MOS gates with typical input currents of less than 10nA. The control input DAC A/DAC B selects which DAC can accept data from the input port. Inputs CS and WR control the operating mode of the selected DAC (Table 1.). When CS and WR
tCS CS tAS DAC A/ DAC B VALID tWR WR tDS DB7-DB0 VALID tDH tAH tCH
are both low the selected DAC is in the write mode. The input data latches of the selected DAC are transparent and its analog output responds to activity on DB0-DB7 (Write mode). The selected DAC latch retains the data which was present on DB0-DB7 just prior to CS or WR assuming a high state. Both analog outputs remain at the values corresponding to the data in their respective latches (Hold mode).
DAC A/ DAC B
L H X X L = Low State
CS
WR
DAC A
WRITE HOLD HOLD HOLD X = Don't Care
DAC B
HOLD WRITE HOLD HOLD
L L L L H X X H H = High State
NOTE: 1. Timing measured from (VIH + VIL) /2
Figure 1. Write Cycle Timing Diagram
Table 1. DACs Mode Selection
MICROPROCESSOR INTERFACE
NOTE: 8085 instruction shld (store H & L direct) can update both DACS with data from H and L registers A0-A15 A** www..com VMA CPU 6800
ADDRESS DECODE LOGIC
ADDRESS BUS DAC A/DAC B CS A+1*** WR DB0 DB7
DAC A
A8-A15 A** CPU 8085 WR ALE AD0-AD7
ADDRESS DECODE LOGIC
ADDRESS BUS DAC A/DAC B CS A+1***
LATCH 8212 DAC A
2
MP7529A*
DAC B
WR DB0 DB7
MP7529A*
DAC B
D0-D7
DATA BUS
ADDR/DATA BUS *Analog circuitry has been omitted for clarity **A = Decoded 7529A DAC A Address ***A+1 = Decoded 7529A DAC B Address
*Analog circuitry has been omitted for clarity **A = Decoded 7529A DAC A Address ***A+1 = Decoded 7529A DAC B Address
Figure 2. MP7529A Dual DAC to 6800 CPU Interface
Figure 3. MP7529A Dual DAC to 8085 CPU Interface
Rev. 2.00 5
MP7529A
PERFORMANCE CHARACTERISTICS
Graph 1. Relative Accuracy vs. Digital Code
APPLICATION NOTES Refer to Section 8 for Applications Information
www..com
Rev. 2.00 6
MP7529A
20 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S20
D
20
11
E
H
10
h x 45 C Seating Plane e B A1 L A
www..com SYMBOL A A1 B C D E e H h L
INCHES MIN 0.097 0.0050 0.014 0.0091 0.500 0.292 MAX 0.104 0.0115 0.019 0.0125 0.510 0.299
MILLIMETERS MIN 2.464 0.127 0.356 0.231 12.70 7.42 MAX 2.642 0.292 0.483 0.318 12.95 7.59
0.050 BSC 0.400 0.010 0.016 0 0.410 0.016 0.035 8
1.27 BSC 10.16 0.254 0.406 0 10.41 0.406 0.889 8
Rev. 2.00 7
MP7529A
20 LEAD PLASTIC LEADED CHIP CARRIER (PLCC) P20
D D1 A2 Seating Plane
1
D
D1 e1
B D2
D3 A
C A1
www..com SYMBOL A A1 A2 B C D D1 (1) D2 D3 e1 Note: (1)
INCHES MIN 0.165 0.100 0.148 0.013 0.008 0.385 0.350 0.290 MAX 0.180 0.110 0.156 0.021 0.012 0.395 0.354 0.330
MILLIMETERS MIN 4.19 2.54 3.76 0.330 0.203 9.78 8.89 7.37 MAX 4.57 2.79 3.96 0.533 0.305 10.03 8.99 8.38
0.200 Ref 0.050 BSC
5.08 Ref. 1.27 BSC
Dimension D1 does not include mold protrusion. Allowed mold protrusion is 0.254 mm/0.010 in.
Rev. 2.00 8
MP7529A
20 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) N20
S
20 1 Q1 D
11 10 E1 E A1
Seating Plane
A L B e B1
C
INCHES SYMBOL A A1 www..com B B1 (1) C D E E1 e L MIN -- 0.015 0.014 0.038 0.008 0.945 0.295 0.220 MAX 0.200 -- 0.023 0.065 0.015 1.060 0.325 0.310
MILLIMETERS MIN -- 0.38 0.356 0.965 0.203 24.0 7.49 5.59 MAX 5.08 -- 0.584 1.65 0.381 26.92 8.26 7.87
0.100 BSC 0.115 0 0.055 0.040 (1) 0.150 15 0.070 0.080
2.54 BSC 2.92 0 1.40 1.02 3.81 15 1.78 2.03
Q1 S Note:
The minimum limit for dimensions B1 may be 0.023" (0.58 mm) for all four corner leads only.
Rev. 2.00 9
MP7529A Notes
www..com
Rev. 2.00 10
MP7529A Notes
www..com
Rev. 2.00 11
MP7529A
www..com
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.00 12

▲Up To Search▲

Price & Availability of MP7529A

	To Download MP7529A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .